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Minor MIPS III/IV tune-up.
This commit is contained in:
Andy Polyakov
parent
7b65c3298f
commit
0bbd03525e
@ -154,11 +154,11 @@ my %table=(
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# Only N32 and N64 ABIs are supported. If you need O32 ABI build, invoke
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# './Configure irix-[g]cc' manually.
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# -mips4 flag is added by ./config when appropriate.
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"irix-mips3-gcc","gcc:-mabi=n32 -mmips-as -O3 -DTERMIOS -DB_ENDIAN::(unknown)::MD2_CHAR RC4_INDEX RC4_CHAR DES_UNROLL DES_RISC2 DES_PTR BF_PTR SIXTY_FOUR_BIT:asm/mips3.o::",
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"irix-mips3-cc", "cc:-n32 -O2 -use_readonly_const -DTERMIOS -DB_ENDIAN::(unknown)::DES_PTR DES_RISC2 DES_UNROLL BF_PTR SIXTY_FOUR_BIT:asm/mips3.o::",
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"irix-mips3-gcc","gcc:-mabi=n32 -mmips-as -O3 -DTERMIOS -DB_ENDIAN -DBN_DIV3W::(unknown)::MD2_CHAR RC4_INDEX RC4_CHAR DES_UNROLL DES_RISC2 DES_PTR BF_PTR SIXTY_FOUR_BIT:asm/mips3.o::",
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"irix-mips3-cc", "cc:-n32 -O2 -use_readonly_const -DTERMIOS -DB_ENDIAN -DBN_DIV3W::(unknown)::DES_PTR DES_RISC2 DES_UNROLL BF_PTR SIXTY_FOUR_BIT:asm/mips3.o::",
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# N64 ABI builds.
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"irix64-mips4-gcc","gcc:-mabi=64 -mips4 -mmips-as -O3 -DTERMIOS -DB_ENDIAN::(unknown)::DES_RISC2 DES_UNROLL SIXTY_FOUR_BIT_LONG:asm/mips3.o::",
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"irix64-mips4-cc", "cc:-64 -mips4 -O2 -use_readonly_const -DTERMIOS -DB_ENDIAN::(unknown)::DES_RISC2 DES_UNROLL SIXTY_FOUR_BIT_LONG:asm/mips3.o::",
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"irix64-mips4-gcc","gcc:-mabi=64 -mips4 -mmips-as -O3 -DTERMIOS -DB_ENDIAN -DBN_DIV3W::(unknown)::DES_RISC2 DES_UNROLL SIXTY_FOUR_BIT_LONG:asm/mips3.o::",
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"irix64-mips4-cc", "cc:-64 -mips4 -O2 -use_readonly_const -DTERMIOS -DB_ENDIAN -DBN_DIV3W::(unknown)::DES_RISC2 DES_UNROLL SIXTY_FOUR_BIT_LONG:asm/mips3.o::",
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# HPUX 9.X config.
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# Don't use the bundled cc. It is broken. Use HP ANSI C if possible, or
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@ -395,32 +395,32 @@ LEAF(bn_add_words)
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.L_bn_add_words_loop:
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ld ta0,0(a2)
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ld t1,8(a1)
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ld ta1,8(a2)
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ld t2,16(a1)
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ld ta2,16(a2)
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ld t3,24(a1)
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ld ta3,24(a2)
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daddu ta0,t0
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subu a3,4
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ld t1,8(a1)
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and AT,a3,MINUS4
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ld t2,16(a1)
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PTR_ADD a2,32
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ld t3,24(a1)
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PTR_ADD a0,32
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ld ta1,-24(a2)
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PTR_ADD a1,32
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ld ta2,-16(a2)
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ld ta3,-8(a2)
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daddu ta0,t0
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sltu t8,ta0,t0
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daddu t0,ta0,v0
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PTR_ADD a0,32
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sltu v0,t0,ta0
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sd t0,-32(a0)
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daddu v0,t8
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daddu ta1,t1
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PTR_ADD a1,32
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sltu t9,ta1,t1
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daddu t1,ta1,v0
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PTR_ADD a2,32
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sltu v0,t1,ta1
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sd t1,-24(a0)
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daddu v0,t9
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daddu ta2,t2
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and AT,a3,MINUS4
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sltu t8,ta2,t2
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daddu t2,ta2,v0
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sltu v0,t2,ta2
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@ -495,25 +495,26 @@ LEAF(bn_sub_words)
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.L_bn_sub_words_loop:
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ld ta0,0(a2)
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subu a3,4
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ld t1,8(a1)
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ld ta1,8(a2)
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and AT,a3,MINUS4
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ld t2,16(a1)
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ld ta2,16(a2)
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PTR_ADD a2,32
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ld t3,24(a1)
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ld ta3,24(a2)
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PTR_ADD a0,32
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ld ta1,-24(a2)
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PTR_ADD a1,32
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ld ta2,-16(a2)
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ld ta3,-8(a2)
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sltu t8,t0,ta0
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dsubu t0,ta0
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subu a3,4
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dsubu ta0,t0,v0
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and AT,a3,MINUS4
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sd ta0,0(a0)
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sd ta0,-32(a0)
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MOVNZ (t0,v0,t8)
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sltu t9,t1,ta1
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dsubu t1,ta1
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PTR_ADD a0,32
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dsubu ta1,t1,v0
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PTR_ADD a1,32
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sd ta1,-24(a0)
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MOVNZ (t1,v0,t9)
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@ -521,7 +522,6 @@ LEAF(bn_sub_words)
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sltu t8,t2,ta2
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dsubu t2,ta2
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dsubu ta2,t2,v0
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PTR_ADD a2,32
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sd ta2,-16(a0)
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MOVNZ (t2,v0,t8)
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@ -574,6 +574,51 @@ END(bn_sub_words)
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#undef MINUS4
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.align 5
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LEAF(bn_div_3_words)
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.set reorder
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move a3,a0 /* we know that bn_div_words doesn't
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* touch a3, ta2, ta3 and preserves a2
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* so that we can save two arguments
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* and return address in registers
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* instead of stack:-)
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*/
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ld a0,(a3)
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move ta2,a1
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ld a1,-8(a3)
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move ta3,ra
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move v1,zero
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li v0,-1
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beq a0,a2,.L_bn_div_3_words_skip_div
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bal bn_div_words
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move ra,ta3
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.L_bn_div_3_words_skip_div:
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dmultu ta2,v0
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ld t2,-16(a3)
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move ta0,zero
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mfhi t1
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mflo t0
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sltu t8,t1,v1
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.L_bn_div_3_words_inner_loop:
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bnez t8,.L_bn_div_3_words_inner_loop_done
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sgeu AT,t2,t0
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seq t9,t1,v1
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and AT,t9
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sltu t3,t0,ta2
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daddu v1,a2
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dsubu t1,t3
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dsubu t0,ta2
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sltu t8,t1,v1
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sltu ta0,v1,a2
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or t8,ta0
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.set noreorder
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beqzl AT,.L_bn_div_3_words_inner_loop
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dsubu v0,1
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.set reorder
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.L_bn_div_3_words_inner_loop_done:
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jr ra
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END(bn_div_3_words)
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.align 5
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LEAF(bn_div_words)
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.set noreorder
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@ -633,16 +678,16 @@ LEAF(bn_div_words)
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seq t8,HH,t1
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sltu AT,HH,t1
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and t2,t8
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sltu v0,t0,a2
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or AT,t2
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.set noreorder
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beqz AT,.L_bn_div_words_inner_loop1_done
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sltu t2,t0,a2
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.set reorder
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dsubu QT,1
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dsubu t1,v0
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dsubu t0,a2
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dsubu t1,t2
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b .L_bn_div_words_inner_loop1
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.L_bn_div_words_inner_loop1_done:
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dsubu QT,1
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.set reorder
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.L_bn_div_words_inner_loop1_done:
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dsll a1,32
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dsubu a0,t3,t0
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@ -655,6 +700,7 @@ LEAF(bn_div_words)
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ddivu zero,a0,DH
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mflo QT
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.L_bn_div_words_skip_div2:
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#undef DH
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dmultu a2,QT
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dsll t3,a0,32
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dsrl AT,a1,32
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@ -666,69 +712,26 @@ LEAF(bn_div_words)
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seq t8,HH,t1
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sltu AT,HH,t1
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and t2,t8
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sltu v1,t0,a2
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or AT,t2
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.set noreorder
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beqz AT,.L_bn_div_words_inner_loop2_done
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sltu t2,t0,a2
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.set reorder
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dsubu QT,1
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dsubu t1,v1
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dsubu t0,a2
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dsubu t1,t2
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b .L_bn_div_words_inner_loop2
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dsubu QT,1
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.set reorder
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.L_bn_div_words_inner_loop2_done:
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#undef HH
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dsubu a0,t3,t0
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or v0,QT
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dsrl v1,a0,t9 /* v1 contains remainder if anybody wants it */
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dsrl a2,t9 /* restore a2 */
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jr ra
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#undef HH
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#undef DH
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#undef QT
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END(bn_div_words)
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.align 5
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LEAF(bn_div_3_words)
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.set reorder
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move a3,a0 /* we know that bn_div_words doesn't
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* touch a3, ta2, ta3 and preserves a2
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* so that we can save two arguments
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* and return address in registers
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* instead of stack:-)
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*/
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ld a0,(a3)
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move ta2,a2
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move a2,a1
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ld a1,-8(a3)
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move ta3,ra
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move v1,zero
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li v0,-1
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beq a0,a2,.L_bn_div_3_words_skip_div
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jal bn_div_words
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move ra,ta3
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.L_bn_div_3_words_skip_div:
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dmultu ta2,v0
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ld t2,-16(a3)
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mflo t0
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mfhi t1
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.L_bn_div_3_words_inner_loop:
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sgeu AT,t2,t0
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seq t9,t1,v1
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sltu t8,t1,v1
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and AT,t9
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or AT,t8
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bnez AT,.L_bn_div_3_words_inner_loop_done
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daddu v1,a2
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sltu t3,t0,ta2
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sltu AT,v1,a2
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dsubu v0,1
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dsubu t0,ta2
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dsubu t1,t3
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beqz AT,.L_bn_div_3_words_inner_loop
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.L_bn_div_3_words_inner_loop_done:
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jr ra
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END(bn_div_3_words)
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#define a_0 t0
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#define a_1 t1
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#define a_2 t2
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@ -202,7 +202,7 @@ int BN_div(BIGNUM *dv, BIGNUM *rm, const BIGNUM *num, const BIGNUM *divisor,
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{
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BN_ULONG q,l0;
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#ifdef BN_DIV3W
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q=bn_div_3_words(wnump,d0,d1);
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q=bn_div_3_words(wnump,d1,d0);
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#else
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#if !defined(NO_ASM) && !defined(PEDANTIC)
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@ -291,8 +291,8 @@ int BN_div(BIGNUM *dv, BIGNUM *rm, const BIGNUM *num, const BIGNUM *divisor,
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#endif
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}
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#endif /* !BN_DIV3W */
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wnum.d--; wnum.top++;
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l0=bn_mul_words(tmp->d,sdiv->d,div_n,q);
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wnum.d--; wnum.top++;
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tmp->d[div_n]=l0;
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for (j=div_n+1; j>0; j--)
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if (tmp->d[j-1]) break;
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